1. Field of the Invention
The invention relates to a semiconductor device and a fabricating method thereof and more particularly to a dynamic random access memory cell and a dynamic random access memory cell array having vertical channel transistor.
2. Description of Related Art
With the function of computer micro-processors becomes more powerful, the number of programs and operations performed by software becomes greater. Thus, the fabrication technology of memory has become one of the most important technologies in the semiconductor industry. Dynamic random access memory (DRAM) is a volatile memory constituted by a plurality of memory cells. Each of the memory cells is mainly formed by a transistor and a capacitor. Moreover, each of the memory cells is electrically connected to one another through word lines (WLs) and bit lines (BLs).
Along with the development of technology and under demands for size reduction of devices, the length of the channel region in the transistor of DRAM is gradually shortened for the devices to operate faster. However, this leads to problems such as severe short channel effect and on current reduction of transistors.
Therefore, a conventional method for solving the above problems includes changing the transistor in the horizontal direction into the transistor in the vertical direction. In the structure of DRAM, the vertical transistor is fabricated in the trench and the embedded BLs and the embedded WLs are formed.
In one method of disposing the embedded BLs, the doped region is directly formed in the semiconductor substrate. However, the embedded BLs formed by the doped region have higher resistance and cannot enhance the performance of devices. The fabrication becomes more difficult when the doping concentration and doping depth are increased to lower the resistance of the embedded BLs.
In another method of disposing the embedded BLs, the metal embedded BLs are formed. However, the fabrication of the metal embedded BLs is complicated. Moreover, when operating DRAM, severe coupling noise may be generated between two adjacent embedded BLs so as to affect the performance of devices.